Typical integrated circuit fabrication processes involve the initial formation of transistors in a substrate (typically of semiconductor material). The transistors are interconnected by layers of conductive wiring, often referred to as "runners." The conductive wiring layers are separated by dielectrics, often termed "interlevel dielectrics."
Those concerned with the development of integrated circuit technology have engaged in a continuous search for interlevel dielectrics which will fill small spaces between adjacent runners (i.e., fill high aspect ratio spaces) and which are resistant to moisture absorption or creation. Inadequate filling of high aspect ratio spaces means that adjacent conductive wiring lines are not adequately separated from each other. Furthermore, should the dielectric attract or promote the formation of moisture, conductive wiring materials such as aluminum may be ultimately degraded, thereby adversely affecting circuit performance. These problems are exacerbated as circuit dimensions shrink, for example, in the submission range.